1. Field of the Invention
This invention relates generally to behavior modeling, and more particularly to modeling concurrent behavior in a sequential programming environment.
2. Description of the Related Art
Hardware description languages (HDLs) are used to simulate or model electronic circuits and systems. Examples of HDLs include Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and VERILOG. HDLs are concurrent in nature, meaning that multiple operations occur in parallel at the same time. Because HDLs are based on the principle of concurrence, they are capable of describing and modeling many different processes which are running simultaneously. For example, a RTL language may be used to model or simulate a system or circuit by utilizing a hierarchy that includes multiple entities (Boolean equations, registers, control logic, complex event sequences) corresponding to various parts of the modeled circuit or system. During simulation, these multiple entities operate in parallel in a timed manner that may be adjusted by the user to simulate the system or circuit.
In the past, VHDL language simulations have been implemented using relatively expensive UNIX-based Application Specific Integrated Circuit (ASIC) tools. These bit and clock cycle-accurate UNIX-based simulations are typically lengthy and time consuming to run. PC-based simulators have been developed that utilize a graphical user interface (GUI) and offer VHDL and Verilog language simulation capabilities. However, such PC-based simulators are typically large programs that consume large amounts of memory to function. They also require expensive licenses to operate.